3D Imaging Becomes Critical as Chipmakers Shift to Vertical Stacking

Vertical architectures outpace 2D analysis

Semiconductor manufacturers racing to meet AI infrastructure demand are stacking silicon dies vertically to boost bandwidth and energy efficiency. But this shift to three-dimensional chip architectures—from high-bandwidth memory (HBM) assemblies to gate-all-around transistors—has exposed a fundamental weakness in how defects are found and analyzed.

Traditional two-dimensional imaging collapses subsurface features into a single plane, making it difficult to pinpoint voids, delaminations, and cracks that span multiple layers. When a defect appears ambiguous in a 2D cross-section, analysis teams cycle through repeated imaging runs, delaying root cause determination and slowing corrective action on the fab floor. As one layer's failure can degrade an entire stack's yield, the cost of missed or misinterpreted defects climbs sharply.

According to a recent industry article by Adam Stokes of Thermo Fisher Scientific, published on All About Circuits, automated 3D reconstruction and precise planar imaging are shifting from specialized techniques to production requirements.

Why it matters

Global semiconductor sales are forecast to reach approximately $1.5 trillion in 2026, with memory accounting for more than $800 billion, according to the World Semiconductor Trade Statistics organization cited in the article. As manufacturers scale vertically to meet performance targets—logic progressing from FinFET to gate-all-around to complementary FET, DRAM structures becoming increasingly three-dimensional—the gap between what 2D imaging can reveal and what fabs need to know widens. Without scalable 3D analysis, chipmakers risk slower yield learning, more rework loops, and false confidence from incomplete evidence.

3D imaging delivers five times the defect sensitivity

Advanced 3D imaging methods have demonstrated five times the gains in defect sensitivity compared to 2D approaches, according to research from the National Institute of Standards and Technology referenced in the source material. Three-dimensional reconstruction allows engineers to trace how voids propagate, whether they interconnect across layers, and how cracks grow through interfaces—details that remain ambiguous or invisible in traditional cross-sections.

For high-bandwidth memory, where multiple dies must work in concert and each layer must meet strict yield thresholds, known-good die screening supported by 3D analysis helps ensure stack integrity. The technology also bridges length scales, enabling users to locate small defects—such as through-silicon vias under five micrometers in diameter—within large imaging volumes.

Automation addresses the throughput challenge

The primary obstacle to widespread 3D adoption has been time. Generating volumetric reconstructions traditionally takes longer than capturing a single 2D slice. Manufacturers are now pairing automation and artificial intelligence with scanning electron microscopes and focused ion beam systems to remove manual bottlenecks, flag defects earlier, and optimize multi-step processes without sacrificing image quality.

As IMEC data cited in the article indicates, 3D buffer memory is projected to provide five times more bit density than dynamic random-access memory is expected to offer by 2030. Meeting that density while maintaining yield requires imaging workflows that can keep pace with increasingly complex vertical structures.

Industry adoption accelerates

Semiconductor manufacturers that invest deliberately in automated 3D reconstruction and the supporting workflows will be best positioned as AI and wireless technologies drive further architectural complexity, according to Stokes. The shift is already underway: 3D analysis is moving from a competitive advantage to a baseline capability for fabs targeting advanced nodes and high-performance packaging.

These details were first reported by Adam Stokes of Thermo Fisher Scientific in an article published on All About Circuits.