Chip Giants Build Their Own AI Tools, Bypassing EDA Vendors

The world's largest chip makers are no longer waiting for electronic design automation vendors to deliver AI-powered tools. Instead, they're building their own intelligence layers on top of the simulation, verification, and implementation engines they already license—a shift that's redefining the boundary between vendor platforms and customer innovation.

This trend emerged clearly at DAC 2026's Engineering Track, where working engineers presented deployed AI systems built in-house. Samsung, IBM, Texas Instruments, and Renesas all showcased custom AI frameworks that treat commercial EDA tools as computational engines while keeping the intelligence layer proprietary.

The DIY approach in practice

Samsung Electronics engineers presented a reinforcement learning agent that tunes system-on-chip quality-of-service parameters—arbitration priorities, bandwidth allocations—across emulation environments. Using Deep Q-Networks with modern RL enhancements, the system discovers settings that outperform manual methods by exploring design spaces no human team could sweep exhaustively.

The architecture is telling: Samsung built the optimization model themselves, purpose-fitted to their architectures and performance targets, while the execution infrastructure that makes exploration trustworthy comes from existing EDA platforms.

IBM deployed agentic workflows for verification debug that integrate design specifications, HDL, waveforms, and coverage data through Model Context Protocol servers. The company reports 15% to 40% reductions in manual effort on failure triage. A second IBM paper described an agentic framework that generates EDA utilities from user specifications, compressing what would take an estimated four person-weeks into under 30 minutes.

Confidentiality requirements drive much of this in-house development. Samsung teams presented on-premises LLMs that monitor emulation regressions and classify kernel panics, plus multi-agent pipelines built with retrieval-augmented generation specifically so design data never leaves company walls.

Vendor AI still has a role

The same conference track also documented users adopting vendor-supplied AI tools—particularly for problems common across the industry. Presentations covered Cadence power-grid reinforcement tools, Synopsys thermal analysis for 3D integrated circuits, and Siemens library quality assurance frameworks.

The division is logical: Where problems are deeply proprietary—a company's specific SoC behavior, internal debug knowledge, confidential failure patterns—the AI stays homegrown. Where challenges are universal—IR drop closure, thermal analysis—vendor AI wins on economics.

Why it matters

This split creates a strategic tension for EDA vendors. Their tools are becoming computational substrates rather than complete solutions, with the highest-value intelligence layer increasingly built by customers. The boundary between vendor platform and customer IP will likely determine EDA business models for the next five years. It also means the most advanced AI-driven design techniques remain behind corporate firewalls, where lessons learned at Samsung or Nvidia never propagate to smaller players who lack resources to build equivalent systems.

Frank Schirrmeister, writing in his capacity as DAC Engineering Track program chair, first reported these details for EE Times. He noted that while the most secretive companies—Nvidia, Meta, OpenAI—still don't present their internal design-AI stacks publicly, the visible portion of DIY AI adoption has grown substantially.