AI's Next Bottleneck Is Architecture, Not Compute Power

The integration challenge

As artificial intelligence systems scale beyond data centers into vehicles, robots, and industrial equipment, the semiconductor industry faces a fundamental shift in design priorities. According to Sébastien Dauvé, CEO of French research institute CEA-Leti, the primary constraint is no longer transistor performance but how effectively systems integrate memory, photonics, communications, and sensing capabilities.

"The bottleneck is really architectural," Dauvé told EE Times ahead of Leti Innovation Days 2026 in Grenoble. The challenge centers on moving, storing, and managing data efficiently rather than simply adding computational capacity.

Why it matters

This architectural shift has direct implications for semiconductor roadmaps and capital allocation. Companies investing heavily in advanced process nodes may find diminishing returns if system-level integration problems remain unsolved. For enterprises deploying AI at the edge, the emphasis on memory-compute coupling and energy efficiency will determine which platforms can actually deliver on physical AI applications in manufacturing, healthcare, and autonomous systems.

Physical AI changes design priorities

Dauvé identifies what he calls "physical AI" as a second wave following the data center buildout. Unlike generative AI confined to cloud infrastructure, physical AI interacts directly with the real world through connected devices operating under strict power, latency, reliability, and safety constraints.

This shift pushes intelligence closer to data sources and demands specialized, energy-efficient architectures. The trend is reflected across automotive systems, healthcare devices, defense applications, and industrial automation—markets that will increasingly shape semiconductor development alongside traditional data center requirements.

Memory and compute must converge

Conventional architectures that separate memory and compute into distinct domains are becoming inefficient for AI workloads, Dauvé argues. While new memory technologies like spintronics and FeRAM show promise, the more fundamental requirement is tighter coupling between memory and processing.

"Memory and compute must be more tightly coupled," he said, noting that bringing the two closer together reduces energy and latency penalties associated with data movement across large AI systems.

Optical technologies are gaining importance for similar reasons. As AI clusters grow more distributed, electrical interconnects face mounting challenges in bandwidth and power consumption. Silicon photonics could address data movement both within and between future AI systems.

Energy infrastructure becomes the constraint

Beyond architectural challenges, Dauvé points to energy availability as the next major constraint. Data center energy consumption is rising rapidly, but the issue extends beyond chip efficiency.

"The real issue is the availability of reliable electricity," Dauvé said, noting that some projects are already facing delays or cancellations because energy infrastructure cannot support them. Future AI growth may depend as much on power generation and grid capacity as on semiconductor innovation.

Europe's industrialization challenge

Dauvé believes Europe must translate research leadership into industrial impact, particularly in advanced packaging and heterogeneous integration. He views success by 2030 as building a competitive European ecosystem around these capabilities, extending beyond packaging to include photonics, manufacturing, and cross-industry collaboration.

"We work not only on technology but also very closely with industrial partners and end users," Dauvé said. "This allows us to connect research with real applications and industrial deployment."

The details were first reported by EE Times in an interview conducted by Pat Brans.