Agentic AI, Multi-Physics, and Standards Emerge as Chip Design Pillars

Automation layer meets reality

The semiconductor industry's conversation about agentic AI has moved from theoretical promise to operational friction. At DAC 2026, executives from Nvidia, Synopsys, Intel, and emerging startups converged on three technical challenges that will determine whether AI-driven chip design scales beyond pilot projects: making agents work across vendor boundaries, solving multi-physics simulation bottlenecks, and establishing machine-readable standards that enable interoperability.

Tim Costa, Nvidia's VP and GM for industrial engineering and quantum, framed the shift in human terms during the company's first DAC appearance. Engineers will elevate from tool-level tasks to system-level thinking, he said, as long-running AI agents orchestrate verification, thermal analysis, and implementation flows while maintaining context over multi-day runs.

Ravi Subramaniam, chief product management officer at Synopsys, noted the company has worked on AI tooling since 2017, but recent advances in model context windows have enabled what he called "Level 4" autonomous workflow agents—borrowing the automotive industry's self-driving taxonomy. These agents now handle digital verification workloads that previously required constant human supervision, according to EE Times, which first reported details from the conference floor.

Physics simulation becomes the constraint

Agentic workflows depend on the underlying tools they coordinate, bringing thermal and analog design challenges into sharp focus. Vinci, a startup targeting thermomechanical signoff, claims three orders of magnitude speedup over incumbent flows by training physics foundation models that replace weeks-long simulations. Co-founder and CEO Hardik Kabaria positioned the technology as "ChatGPT of physics" deployed behind corporate firewalls for production semiconductor packages.

Indian startup Maieutic Semiconductors, which raised $6 million, applies a similar approach to analog design knowledge. The company uses what co-founder Ashish Lachhwani calls "Socratic" AI to mine internal data and surface tacit expertise from senior designers—addressing a domain where even five-transistor circuits can require years to optimize.

Lalitha Immaneni, VP of semiconductor R&D at Intel, described design teams "jumping blindly" into complex stacks without adequate multi-physics guidance. She cited cases where poor copper-density data forces foundry mechanical teams to spend three to four weeks cleaning databases before beginning analysis. Intel's response centers on system-technology co-optimization (STCO) built atop package assembly design kits (PADKs) that bundle design rules, reference flows, and verification scripts co-certified with memory and IP vendors.

Standards and business models under pressure

Scaling agentic workflows across tool vendors requires machine-readable specifications. Lu Dai, chairman of the Accellera board, discussed the draft Functional Safety Language (FSL) 1.0 standard, designed to express safety requirements and coverage hooks as metadata that tools can parse directly—similar to unified power format (UPF) for power intent.

Paul Penzes, VP of engineering at Qualcomm, argued that closed systems are untenable when competitive pressure demands mixing tools from different vendors to optimize specific parameters. "We can't afford a closed system because we will not be able to succeed," he said on a Synopsys panel. "Every millimeter matters."

Prith Banerjee, senior VP of innovation at Synopsys, raised a parallel challenge: traditional EDA licensing models break under token-based agent consumption. He suggested the industry must move toward consumption-based pricing, though business model details remain unsettled.

Mark Ren, founder and CEO of Agentrys and former head of Nvidia's design automation research, argued the shift requires a new category—agentic design automation (ADA)—where designers create agents rather than RTL. His company's three-layer platform includes secure tool integration, self-improvement loops, and agent-native tools optimized for interactive reasoning rather than batch runs.

Why it matters

The semiconductor industry faces a complexity crisis: advanced packaging, multi-die integration, and sub-3nm processes have outpaced traditional engineering capacity. Agentic AI promises to decouple product development from headcount constraints, but only if the underlying physics models, cross-vendor interoperability, and economic incentives align. The technical debates at DAC 2026 reveal an industry moving from proofs-of-concept to the harder work of production deployment—where standards, business models, and simulation accuracy determine whether automation delivers on its efficiency claims.

EE Times reported these developments from the DAC 2026 show floor in Long Beach, California.